Shallow junction formation

ABSTRACT

A method of forming junctions in a semiconductor substrate, where a gate dielectric layer is grown on the semiconductor substrate, a gate electrode layer is deposited on the gate dielectric layer, and a sacrificial layer is formed on the gate electrode layer. The sacrificial layer is patterned with a material to cover portions of the sacrificial layer and expose portions of the sacrificial layer. The exposed portions of the sacrificial layer are etched to remove the exposed portions of the sacrificial layer and expose portions of the gate electrode layer. The exposed portions of the gate electrode layer are etched to expose portions of the gate dielectric layer and form a gate electrode having exposed vertical faces. The sacrificial layer and the exposed portions of the gate dielectric layer are impregnated with a first species that inhibits diffusion of oxygen through the sacrificial layer and the exposed portions of the gate dielectric layer. The impregnation is accomplished using a process that does not impregnate a significant amount of the first species in the exposed vertical faces of the gate electrode. The impregnated sacrificial layer, the exposed vertical faces of the gate electrode, and the impregnated exposed portions of the gate dielectric layer are exposed to an oxidizing environment, causing oxide growth on at least the exposed vertical faces of the gate electrode, and thereby covering the vertical faces of the gate electrode with oxide sidewalls. However, the oxidizing environment does not cause significant oxide growth under the impregnated sacrificial layer and the impregnated exposed portions of the gate dielectric layer. A second species is impregnated through the impregnated exposed portions of the gate dielectric layer into portions of the semiconductor substrate that underlie the impregnated exposed portions of the gate dielectric layer. The impregnated second species forms junctions in the portions of the semiconductor substrate that underlie the impregnated exposed portions of the gate dielectric layer.

This is a divisional of application Ser. No. 09/670,448 filed Sep. 26,2000 now U.S. Pat. No. 6,486,064.

TECHNICAL FIELD

This invention relates to the field of semiconductor processing. Moreparticularly, this invention relates to a method for forming a shallowjunction for an integrated circuit.

BACKGROUND OF THE INVENTION

As lateral integrated circuit device geometries continue to shrink, itoften is desirable to commensurately shrink certain vertical geometriesof the integrated circuits as well. As the vertical geometries shrink,or in other words as the various layers and structures become thinner,it tends to become increasingly important to control the processes bywhich the layers and structures are formed. This is because there tendsto be less tolerance to variation in the thickness of a relativelythinner structure than there is to variation in the thickness of arelatively thicker structure.

For example, when fabricating integrated circuits such as complimentarymetal oxide semiconductors, it is typically desirable to form the sourceand the drain regions with shallow junction depths in the semiconductorsubstrate. An oxide layer of from about one hundred angstroms to abouttwo hundred angstroms in thickness is typically deposited over thesurface of the semiconductor substrate at some point prior to theimplant that forms the junctions, to protect the semiconductor substratefrom damage during the implant. The sources and drains are commonlyformed by implanting a dopant such as boron or arsenic, depending on thetype of junction being formed. These species are typically implanted atan energy of about one thousand electron volts. At this energy, thedopants have a projected total implant depth of a few hundred angstroms.Thus, the thickness of the protective oxide layer plays a verysignificant part in determining the junction depth for sources anddrains formed by the implant.

However, there are other design goals that compete with the design goalof maintaining a uniform and known thickness of the protective oxidelayer. For example, a polysilicon gate electrode reoxidation process istypically conducted immediately after the polysilicon gate electrode isetched. The reoxidation process is primarily designed to grow oxidesidewalls, on the vertical faces of the polysilicon gate electrode, toprotect the polysilicon gate electrode during subsequent processing.Unfortunately, the reoxidation process tends to also grow additionaloxide at the interface between the semiconductor substrate and theprotective oxide layer, thus increasing the thickness of the protectiveoxide layer by some amount. The additional thickness of the protectiveoxide layer effects the depth to which the dopant for the source anddrain regions is implanted into the semiconductor substrate, asexplained above.

Thus, there is a need for a method of forming junctions in asemiconductor substrate, where the thickness of the protective layeroverlying the semiconductor substrate does not increase during thereoxidation of the gate electrode layer.

SUMMARY OF THE INVENTION

The above and other needs are met by a method of forming junctions in asemiconductor substrate, where a gate dielectric layer is deposited onthe semiconductor substrate, a gate electrode layer is deposited on thegate dielectric layer, and a sacrificial layer is formed on the gateelectrode layer. The sacrificial layer is patterned with a material tocover portions of the sacrificial layer and expose portions of thesacrificial layer. The exposed portions of the sacrificial layer areetched to remove the exposed portions of the sacrificial layer andexpose portions of the gate electrode layer. The exposed portions of thegate electrode layer are etched to expose portions of the gatedielectric layer and form a gate electrode having exposed verticalfaces.

The sacrificial layer and the exposed portions of the gate dielectriclayer are impregnated with a first species that inhibits diffusion ofoxygen through the sacrificial layer and the exposed portions of thegate dielectric layer. The impregnation is accomplished using a processthat does not impregnate a significant amount of the first species inthe exposed vertical faces of the gate electrode. The impregnatedsacrificial layer, the exposed vertical faces of the gate electrode, andthe impregnated exposed portions of the gate dielectric layer areexposed to an oxidizing environment, causing oxide growth on at leastthe exposed vertical faces of the gate electrode, and thereby coveringthe vertical faces of the gate electrode with oxide sidewalls. However,the oxidizing environment does not cause significant oxide growth underthe impregnated sacrificial layer and the impregnated exposed portionsof the gate dielectric layer.

A second species is impregnated through the impregnated exposed portionsof the gate dielectric layer into portions of the semiconductorsubstrate that underlie the impregnated exposed portions of the gatedielectric layer. The impregnated second species forms junctions in theportions of the semiconductor substrate that underlie the impregnatedexposed portions of the gate dielectric layer.

Thus, in this manner junctions with very controlled junction depths areformed in the semiconductor substrate. Because the gate dielectric layeris impregnated with the first species that inhibits diffusion of oxygen,the gate dielectric layer does not appreciably grow in thickness duringthe oxidation process by which the sidewalls on the gate electrode layerare formed. By maintaining the gate dielectric layer at a knownthickness, the results of the process by which the second species isimpregnated into the semiconductor substrate are more repeatable, andthe junctions can be formed to a finely controlled depth within thesemiconductor substrate.

In various preferred embodiments of the invention the semiconductorsubstrate is monocrystalline silicon, the gate dielectric layer issilicon oxide, the gate electrode layer is polysilicon, and thesacrificial layer is silicon oxide. Most preferably the first species isnitrogen that is impregnated to a concentration of between about threeatomic percent and about twenty atomic percent. Also in the preferredembodiment, the impregnated exposed portions of the gate dielectriclayer are cleaned prior to the step of impregnating the second species.

BRIEF DESCRIPTION OF THE DRAWINGS

Further advantages of the invention will become apparent by reference tothe detailed description of preferred embodiments when considered inconjunction with the following drawings, which are not to scale so as tomore clearly depict the details, wherein like reference charactersdesignate like or similar elements throughout the several views, andwherein:

FIG. 1 is a cross sectional view of an integrated circuit having asemiconductor substrate covered with a gate dielectric layer, that iscovered with a gate electrode layer,

FIG. 2 is a cross sectional view of the integrated circuit of FIG. 1,where a sacrificial layer has been deposited,

FIG. 3 is a cross sectional view of the integrated circuit of FIG. 2,where the sacrificial layer and the gate electrode layer have beenetched and the gate dielectric layer has been cleaned,

FIG. 4 is a cross sectional view of the integrated circuit of FIG. 3,where an oxygen diffusion inhibiting species is being impregnated,

FIG. 5 is a cross sectional view of the integrated circuit of FIG. 4,where oxide sidewalls have been grown on the exposed vertical faces ofthe gate electrode layer, and

FIG. 6 is a cross sectional view of the integrated circuit of FIG. 5,where the pocket and source/drain implants have been made.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to FIG. 1, there is depicted a portion of a semiconductorsubstrate 12, that has received some amount of processing to formvarious structures within and on top of the semiconductor substrate 12.As described herein, the specific example of a monocrystalline siliconsubstrate 12 is used. However, it is appreciated that this is by way ofexample only and that in various alternate embodiments substrates ofother materials can be used. Further, the various specific embodimentspresented in regard to the different structures that are formed are alsogiven not by way of limitation, but by way of example, and various otherembodiments are possible as well. As depicted in the figures, theinvention is described herein with particular reference to one of eitheran NMOS or a PMOS integrated circuit 10, which forms a part of a largerCMOS integrated circuit.

As depicted in FIG. 1, isolation structures 16 have been formed in thesemiconductor substrate 12. In the preferred embodiment, the isolationsstructures 16 are formed primarily of silicon oxide according to one ormore of a variety of different methods, such as local oxidation ofsilicon or shallow trench isolation processes. A well 14 has also beenformed in the semiconductor substrate 12. In the preferred embodiments,where the semiconductor substrate 12 is a silicon substrate, the well 14is either an N doped well or a P doped well, depending upon the dopanttype of the surrounding semiconductor substrate 12, whether it be P typeor N type, respectively. The well 14 may be formed according to one ormore of a variety of different methods, such as diffusion ionimplantation.

A gate dielectric layer 18 is grown on the top surface of thesemiconductor substrate 12. In the preferred embodiment the gatedielectric layer 18 is a layer of silicon oxide. As explained in moredetail below, portions of the gate dielectric layer 18 are to be usedfor an insulating layer between a gate electrode that is to be formedand the semiconducting substrate 12 that underlies the gate electrode.The gate dielectric layer 18 is preferably grown to a thickness that isdependent at least in part to the type of source/drain implant that isto be performed. A low energy dopant implant typically uses a lowerthickness of gate dielectric layer 18, in order to avoid dopants beingtrapped in the gate dielectric layer 18, and therefore unable to beactivated in the semiconductor substrate 12.

In the preferred embodiment of an integrated circuit 10 in which a lowenergy dopant implant is to be accomplished, the gate dielectric layer18 is grown to a thickness of between about ten angstroms and about twohundred angstroms, and most preferably about thirty-five angstroms. Thegate dielectric layer 18 is grown according to one or more differentoxidation techniques, such as dry oxidation and wet oxidation, includingmethods to harden the gate dielectric layer 18 against boronpenetration, such as a subsequent oxidation step in a NO ambientenvironment.

A gate electrode layer 20 is deposited on the top surface of the gatedielectric layer 18. In the preferred embodiment the gate electrodelayer 20 is a layer of polysilicon. In the preferred embodiments, thegate electrode layer 20 is deposited to a thickness of between aboutfive hundred angstroms and about three thousand angstroms, and mostpreferably about eighteen hundred angstroms. The gate electrode layer isdeposited according to one or more different deposition techniques, suchas physical vapor deposition and chemical vapor deposition. One purposeof the gate electrode layer 20 is that it is eventually used to form thegate electrode for the integrated circuit 10.

As depicted in FIG. 2, a sacrificial layer 22 is deposited or grown onthe top surface of the gate electrode layer 20. In the preferredembodiment the sacrificial layer 22 is a layer of silicon oxide. In thepreferred embodiments, the sacrificial layer 22 is deposited to athickness of between about thirty angstroms and about three hundredangstroms, and most preferably about one hundred angstroms. Thesacrificial layer 22 is deposited or grown according to one or moredifferent deposition or oxide growth techniques, such as physical vapordeposition, chemical vapor deposition, dry oxidation, and wet oxidation.One purpose of the sacrificial layer 22 is that it is eventually used topattern and protect the gate electrode layer 20.

The sacrificial oxide layer 22 is patterned according to one or more ofa variety of different methods. For example, in a preferred embodimentthe sacrificial oxide layer 22 is patterned by overlaying it with alayer of photoresist that is cured, exposed, developed, and baked. Theimage patterned in the photoresist thus leaves portions of thesacrificial layer 22 exposed and other portions of the sacrificial layer22 covered. The exposed portions of the sacrificial layer 22 are thenetched to expose the gate electrode layer 20 in the portions of the gateelectrode layer 20 that underlie the exposed and etched portions of thesacrificial layer 22.

The sacrificial layer 22 may be etched according to any one or more of avariety of different techniques. In one embodiment the sacrificial layer22 is etched using an etchant that selectively etches the material ofthe sacrificial layer 22 at a significantly faster rate than it etchesthe material of the gate electrode layer 20. For example, in theembodiment where the sacrificial layer 22 is silicon oxide and the gateelectrode layer 20 is polysilicon, a wet etch in an aqueous solution ofhydrofluoric acid preferentially etches the silicon oxide sacrificiallayer 22 at a rate that is significantly faster than the rate at whichthe solution etches the polysilicon gate electrode layer 20.

In alternate embodiments, the sacrificial layer 22 is etched using anetchant that etches both the sacrificial layer 22 and the gate electrodelayer 20 at substantially the same rate, or at rates that are not sodifferent that etching both the sacrificial layer 22 and the gateelectrode layer 20 at the same time is impractical. For example, in onesuch embodiment both the sacrificial layer 22 and the gate electrodelayer 20 are etched in one process step with a highly directional highdensity plasma etch.

FIG. 3 depicts the integrated circuit 10 at a point where both thesacrificial layer 22 and the gate electrode layer 20 have been etched,regardless of whether they were etched in a single process or multipleprocesses, and the photoresist masking material has been removed fromthe surface of the sacrificial layer 22. It is noted that thephotoresist masking material used to pattern the sacrificial layer 22may be removed at any one of several different points between thebeginning of etching of the sacrificial layer 22 and the end of etchingthe gate electrode layer 20, depending upon the specific etchingtechniques selected for the sacrificial layer 22 and the gate electrodelayer 20, and the compatibility of the photoresist masking material withthose selected etching techniques.

As depicted in FIG. 3, etching the gate electrode layer 20 leavesportions of the gate dielectric layer 18 exposed and other portions ofthe gate dielectric layer 18 covered. In a most preferred embodiment,the gate dielectric layer 18 is cleaned in some manner prior to furtherprocessing. For example, in the embodiment where the gate dielectriclayer 18 is formed of silicon oxide, dipping the integrated circuit inan aqueous solution of hydrofluoric acid for a brief length of time willtend to etch a portion of the silicon oxide gate dielectric layer 18.This cleans the surface of the silicon oxide gate dielectric layer 18 byremoving any impurities that may be left behind on the surface of thesilicon oxide gate dielectric layer 18 from prior processing steps, suchas the etches of the sacrificial layer 22 and the gate electrode layer20.

In a most preferred embodiment, the cleaning of the gate dielectriclayer 18 is conducted so as to remove between about zero angstroms andabout fifty angstroms, and most preferably about ten angstroms of thethickness of the gate dielectric layer 18. The hydrofluoric acidsolution is preferably at room temperature, which is about twenty-onecentigrade.

Cleaning the gate dielectric layer 18 with an isotropic etchant, such asa wet etchant like the hydrofluoric acid solution, tends to undercut thebottom edge of the gate electrode layer 20 to some small degree. Theamount of undercutting as depicted in FIG. 3 is greatly exaggerated, sothat the undercutting can be detected in the drawing. In alternateembodiments where a highly anisotropic etchant is used to clean thesurface of the gate dielectric layer 18, such as a highly directionalion bombardment, the bottom edge of the gate electrode layer 20 tends tonot be undercut to any significant degree.

The integrated circuit 10 is exposed to a first species 24 according toa process by which the first species primarily contacts the horizontalsurfaces of the integrated circuit 10, and preferentially does notappreciably contact the vertical surfaces of the integrated circuit 10.This process is exemplified in FIG. 4. For example, the first species isapplied using a process such as an accelerated plasma having a zerodegree tilt angle. In other words the first species is preferablyionized and accelerated toward the integrated circuit 10 at an anglethat is substantially perpendicular to the plane of the integratedcircuit 10, as determined by the angle at which the semiconductorsubstrate 12 is disposed.

The first species is specifically selected so as to inhibit diffusion ofoxygen through the gate dielectric layer 18. Preferably, the firstspecies also inhibits diffusion of oxygen through the sacrificial layer22. In a preferred embodiment, where both the gate dielectric layer 18and the sacrificial layer 22 are formed of silicon oxide, nitrogen isused as the first species. In alternate embodiments where othermaterials are used to form the gate dielectric layer 18 and thesacrificial layer 22, materials other than nitrogen may be selected,which materials are selected based at least in part upon theircompatibility with the other process steps, such as described above andbelow, and their ability to inhibit diffusion of oxygen through thematerials selected to form the gate dielectric layer 18 and thesacrificial layer 22.

The nitrogen is preferably impregnated into the gate dielectric layer 18and the sacrificial layer 22 to a concentration of between about threeatomic percent and about twenty atomic percent, and most preferablyabout fifteen atomic percent. For example, in a preferred embodiment ofthe method according to the present invention, and to continue theexample introduced above, the gate dielectric layer 18 and thesacrificial layer 22 are exposed to a nitrogen plasma source, whichtends to cause the gate dielectric layer 18 and the sacrificial layer 22to absorb an amount of nitrogen in a nitridation process. Thenitridation process converts the silicon oxide material of the gatedielectric layer 18 and the sacrificial layer 22 to a nitridized siliconoxide barrier layer.

In a most preferred embodiment, the gate dielectric layer 18 and thesacrificial layer 22 are not directly exposed to the nitrogen plasma,rather the nitrogen plasma is remote from the substrate 12 and the gatedielectric layer 18 and the sacrificial layer 22 are exposed to thenitrogen ions via a downstream process. This type of process may beaccomplished in a chamber such as a DPS reactor manufactured by AppliedMaterials of Santa Clara, Calif. The process is preferably accomplishedat a pressure of between about 0.001 Torr and about 1.0 Torr, and mostpreferably about 0.1 Torr, with an ion density of between about threeatomic percent and about thirty atomic percent, and most preferablyabout twenty atomic percent. The process is preferably conducted for aperiod of time of between about two seconds and about ten minutes, andmost preferably about thirty seconds. The radio frequency plasma poweris preferably set between about two hundred watts and about two thousandwatts, and is most preferably set at about one thousand watts. Thesubstrate 10 is biased to provide the preferential acceleration of theions with a bias of between about zero watts and about fifty watts, andmost preferably about ten watts. The temperature at which thenitridation is carried out should stay at or below about 250 centigradeso that neither the apparatus nor the integrated circuits are damagedduring processing.

As previously mentioned, the nitrogen is preferably not applied to theexposed vertical faces of the gate electrode layer 20, for reasons asexplained in more detail hereafter.

The integrated circuit 10 is exposed to an oxidizing environment. Thisis preferably accomplished by exposing the integrated circuit 10 to asource of oxygen at an elevated temperature. The environment may beeither a wet oxidizing environment, or more preferably a dry oxidizingenvironment. As depicted in FIG. 4, when the integrated circuit 10 isexposed to the oxidizing environment, it is actually the exposedportions of the gate dielectric layer 18, the exposed vertical faces ofthe gate electrode layer 20, and the exposed surfaces of the sacrificiallayer 22 that are exposed to the oxidizing environment.

The process by which the integrated circuit 10 is exposed to anoxidizing environment is referred to as a reoxidation process. A primarypurpose of the reoxidation process is to grow oxide sidewalls 26 on theexposed vertical faces of the gate electrode layer 20, as depicted inFIG. 5.

As explained above, the oxidizing environment tends to encourage thegrowth of oxides of those materials that form oxides. In the preferredembodiment, where the gate dielectric layer 18 and the sacrificial layer20 are both formed of silicon oxide, neither the gate dielectric layer18 nor the sacrificial layer 20 tend to oxidize further. However, intypical processing the oxygen in the oxidizing environment tends todiffuse through the silicon oxide of the both the gate dielectric layer18 and the sacrificial layer 20 to the silicon material below therespective silicon oxide layers.

For example, the oxygen typically diffuses through the silicon oxidegate dielectric layer 18 to the interface of the silicon oxide gatedielectric layer 18 and the silicon substrate 12. When such diffusionoccurs, silicon oxide tends to grow at the interface between the siliconoxide gate dielectric layer 18 and the silicon substrate 12, whicheffectively increases the thickness of the silicon oxide gate dielectriclayer 18. As described above, this growth in the thickness of thesilicon oxide gate dielectric layer 18 tends to cause problems withsubsequent processes, such as the formation of the source and drainareas of the integrated circuit 10.

As a further example, when oxygen diffuses through the silicon oxidesacrificial layer 22, silicon oxide tends to grow at the interfacebetween the silicon oxide sacrificial layer 22 and the polysilicon gateelectrode layer 20, which effectively increases the thickness of thesilicon oxide sacrificial layer 22 and decreases the thickness of thepolysilicon gate electrode layer 20.

However, impregnating the sacrificial layer 22 and the gate dielectriclayer 18 with the first species, which in the preferred embodimentdescribed above is nitrogen, tends to inhibit the diffusion of oxygenthrough the sacrificial layer 22 and the gate dielectric layer 18, andthereby inhibits formation of oxides with the materials underlying thesacrificial layer 22 and the gate dielectric layer 18.

For example, the impregnation of nitrogen into the silicon oxide gatedielectric layer 18 tends to inhibit the diffusion of oxygen through thesilicon oxide gate dielectric layer 18 to the interface with the siliconsubstrate 12. Thus, no additional oxide tends to grow at the interfacebetween the silicon oxide gate dielectric layer 18 and the siliconsubstrate 12, because there is substantially no oxygen, or asubstantially reduced amount of oxygen, available to generate the oxidegrowth.

To continue the example, the impregnation of nitrogen into the siliconoxide sacrificial layer 22 tends to inhibit the diffusion of oxygenthrough the silicon oxide sacrificial layer 22 to the interface with thetop surface of the polysilicon gate electrode layer 20. Thus, noadditional oxide tends to grow at the interface between the siliconoxide sacrificial layer 22 and the top surface of the polysilicon gateelectrode layer 20, because there is substantially no oxygen, or asubstantially reduced amount of oxygen, available to generate the oxidegrowth.

Because no substantial additional amount of oxide is grown during thereoxidation process at the interface between the gate dielectric layer18 and the semiconductor substrate 12, the gate dielectric layer 18remains at substantially the same thickness as described above. In thismanner, the variations in thickness of the gate dielectric layer 18, atdifferent points across the surface of the semiconductor substrate 12and at the same point through the processing of the integrated circuit10, remain at a relatively low level. This in turns allows thesubsequently formed source and drain junctions to be placed at arelatively fixed position. This ability to control the source and drainimplants to such a fine degree provides some of the control desired toproduce a shallow junction integrated circuit 10.

FIG. 6 depicts the integrated circuit 10 after the punch throughimplants 28 and one of either the lightly doped drain or highly dopeddrain implants 30 have been performed. Subsequent processing creates thesource and drain electrodes, the insulating layers, the electricalcontacts between the different integrated circuits 10 on thesemiconductor substrate 12, and all the other structures required for afully operable integrated circuit 10.

The process described above can be modified in various embodiments. Forexample, as described above the reoxidation step is performed prior tothe implant of the second species. In this preferred embodiment, theimplanted second species is not subjected to the thermal energy absorbedby the semiconductor substrate 12 during the reoxidation step, whichtends to create some amount of unwanted diffusion within thesemiconductor substrate 12 by the second species. However, otherbenefits of the method as explained are retained when the method isperformed with the reoxidation and the implant of the second speciesreversed. For example, the implant of the second species still inhibitssubsequent oxide growth at both the gate dielectric layer 18 and thesacrificial layer 22. Because the sacrificial layer 22 does not increasein thickness during the reoxidation, the subsequently performed P+polysilicon implantation through the sacrificial layer 22 produces morerepeatable results, in a manner similar to the benefits as describedabove in regard to the source/drain implants.

When the method is performed with the reoxidation performed after thesecond species implant, the reoxidation can be performed for a longerperiod of time, or with other adjusted processing conditions, so as toform thicker oxide sidewalls on the vertical faces of the gate electrode20. The thicker oxide sidewalls are referred to as sidewall oxidespacers, and preferably have a thickness of between about one hundredangstroms and about one thousand angstroms, and most preferably abouttwo hundred angstroms.

Although the description above recites that oxide growth occurs on thevertical faces of the gate electrode 20, it is appreciated that, asdepicted in FIGS. 5 and 6, some amount of oxide growth also occurs atthe outside edges of the interfaces between the gate electrode layer 20and the sacrificial layer 22 and the gate dielectric layer 18. However,this oxide growth at the outside edges of these interfaces is verylimited in comparison to the overall length of these interfaces, and sothe discussion above has simplified the description to state that oxidegrowth occurs at the vertical faces of the gate electrode 20. Asdescribed at length above, the implantation of the first speciessubstantially inhibits oxide growth at these interfaces, along asubstantial interior portion of the length of these interfaces.

The foregoing description of preferred embodiments for this inventionhave been presented for purposes of illustration and description. Theyare not intended to be exhaustive or to limit the invention to theprecise form disclosed. Obvious modifications or variations are possiblein light of the above teachings. The embodiments are chosen anddescribed in an effort to provide the best illustrations of theprinciples of the invention and its practical application, and tothereby enable one of ordinary skill in the art to utilize the inventionin various embodiments and with various modifications as is suited tothe particular use contemplated. All such modifications and variationsare within the scope of the invention as determined by the appendedclaims when interpreted in accordance with the breadth to which they arefairly, legally, and equitably entitled.

What is claimed is:
 1. An integrated circuit, the improvement comprisingjunctions in the integrated circuit formed according to a methodcomprising: growing a gate dielectric layer on the semiconductorsubstrate, depositing a gate electrode layer on the gate dielectriclayer, forming a sacrificial layer on the gate electrode layer,patterning the sacrificial layer with a material to cover portions ofthe sacrificial layer and expose portions of the sacrificial layer,etching the exposed portions of the sacrificial layer to remove theexposed portions of the sacrificial layer and expose portions of thegate electrode layer, etching the exposed portions of the gate electrodelayer to expose portions of the gate dielectric layer and form a gateelectrode having exposed vertical faces, impregnating the sacrificiallayer and the exposed portions of the gate dielectric layer with a firstspecies that inhibits diffusion of oxygen through the sacrificial layerand the exposed portions of the gate dielectric layer, using a processthat does not impregnate a significant amount of the first species inthe exposed vertical faces of the gate electrode, impregnating a secondspecies through the impregnated exposed portions of the gate dielectriclayer into portions of the semiconductor substrate that underlie theimpregnated exposed portions of the gate dielectric layer to formjunctions in the portions of the semiconductor substrate that underliethe impregnated exposed portions of the gate dielectric layer, andexposing the impregnated sacrificial layer, the exposed vertical facesof the gate electrode, and the impregnated exposed portions of the gatedielectric layer to an oxidizing environment, causing oxide growth on atleast the exposed vertical faces of the gate electrode and therebycovering the vertical faces of the gate electrode with sidewall oxidespacers, but not causing significant oxide growth under the impregnatedsacrificial layer and the impregnated exposed portions of the gatedielectric layer.
 2. An integrated circuit, the improvement comprisingjunctions in the integrated circuit formed according to a methodcomprising: growing a gate dielectric layer on the semiconductorsubstrate, depositing a gate electrode layer on the gate dielectriclayer, forming a sacrificial layer on the gate electrode layer,patterning the sacrificial layer with a material to cover portions ofthe sacrificial layer and expose portions of the sacrificial layer,etching the exposed portions of the sacrificial layer to remove theexposed portions of the sacrificial layer and expose portions of thegate electrode layer, etching the exposed portions of the gate electrodelayer to expose portions of the gate dielectric layer and form a gateelectrode having exposed vertical faces, impregnating the sacrificiallayer and the exposed portions of the gate dielectric layer with a firstspecies that inhibits diffusion of oxygen through the sacrificial layerand the exposed portions of the gate dielectric layer, using a processthat does not impregnate a significant amount of the first species inthe exposed vertical faces of the gate electrode, exposing theimpregnated sacrificial layer, the exposed vertical faces of the gateelectrode, and the impregnated exposed portions of the gate dielectriclayer to an oxidizing environment, causing oxide growth on at least theexposed vertical faces of the gate electrode and thereby covering thevertical faces of the gate electrode with oxide sidewalls, but notcausing significant oxide growth under the impregnated sacrificial layerand the impregnated exposed portions of the gate dielectric layer, andimpregnating a second species through the impregnated exposed portionsof the gate dielectric layer into portions of the semiconductorsubstrate that underlie the impregnated exposed portions of the gatedielectric layer to form junctions in the portions of the semiconductorsubstrate that underlie the impregnated exposed portions of the gatedielectric layer.
 3. An integrated circuit, the improvement comprisingjunctions in the integrated circuit formed according to a method offorming oxide sidewalls on exposed vertical sidewalls of a gateelectrode without forming additional oxide on a top of the gateelectrode or on active areas of a semiconductor substrate on which thegate electrode is disposed, the method comprising: growing a gatedielectric layer on the semiconductor substrate, depositing a gateelectrode layer on the gate dielectric layer, forming a sacrificiallayer on the gate electrode layer, patterning the sacrificial layer witha material to cover portions of the sacrificial layer and exposeportions of the sacrificial layer, etching the exposed portions of thesacrificial layer to remove the exposed portions of the sacrificiallayer and expose portions of the gate electrode layer, etching theexposed portions of the gate electrode layer to expose portions of thegate dielectric layer that overly the active areas of the semiconductorsubstrate, and also to form the gate electrode and the exposed verticalfaces of the gate electrode, impregnating the sacrificial layer and theexposed portions of the gate dielectric layer with a first species thatinhibits diffusion of oxygen through the sacrificial layer and theexposed portions of the gate dielectric layer, using a process that doesnot impregnate a significant amount of the first species in the exposedvertical faces of the gate electrode, exposing the impregnatedsacrificial layer, the exposed vertical faces of the gate electrode, andthe impregnated exposed portions of the gate dielectric layer to anoxidizing environment, causing oxide growth on at least the exposedvertical faces of the gate electrode and thereby covering the verticalfaces of the gate electrode with oxide sidewalls, but not causingsignificant oxide growth under the impregnated sacrificial layer, andthe impregnated exposed portions of the gate dielectric layer thatoverly the active areas of the semiconductor substrate, and impregnatinga second species through the impregnated exposed portions of the gatedielectric layer into the active areas of the semiconductor substratethat underlie the impregnated exposed portions of the gate dielectriclayer to form junctions in the portions of the semiconductor substratethat underlie the impregnated exposed portions of the gate dielectriclayer.